HPC Architecture and Performance Engineer – 91962
Berkeley Lab’s Advanced Technologies Group (ATG) has a new exciting opening for a HPC Architecture and Performance Engineer. This position will contribute to an ongoing ATG group effort to develop a complete understanding of the issues that lead to improved application and computer system performance on extreme-scale advanced architectures. As a team member, you will contribute to efforts for National Energy Research Scientific Computing Center (NERSC) in evaluating existing and emerging High Performance Computing (HPC) systems by analyzing the performance characteristics of leading-edge Department of Energy (DOE) Office of Science application codes. This position requires knowledge of computer architecture & technology trends and the ability to determine their implications for NERSC users.
What You Will Do:
• Assess emerging technologies to provide input for HPC system procurements and DOE technology roadmaps.
• Evaluate hardware and software technologies in emerging areas, such as cloud computing and AI, for their potential to be applied to HPC.
• Work with vendors to prioritize, develop and enhance their technologies in order to better meet the needs of DOE Office of Science application codes and workflows.
• Measure and understand the performance and scalability of key scientific applications or workflows that comprise NERSC’s evolving workload on current and future high-performance computing (HPC) and data intensive platforms.
• Develop techniques to assess the needs of the DOE workload in aggregate. Develop models to optimize the trade-offs between different architectural components.
• Prepare timely reports, papers, and lectures describing significant results for dissemination within NERSC and throughout the broader HPC research community.
• Contribute performance-related expertise to cross-team NERSC activities that may involve application performance tuning, workflow optimization, interconnects, storage I/O, and/or data analysis functions.
• Participate in the NERSC selection process for acquisition of next-generation HPC systems.
As Sr. HPC Architecture and Performance Engineer:
• Take a lead role in one or more of the activities described above.
• Provide technical conceptual guidance to other group members and management, suggest directions for investigation, create new opportunities for NERSC, serve as a principal collaborator on major projects, and be responsible for fostering broader community-wide efforts with organizations outside of NERSC and Berkeley Lab.
What is Required:
• B.S. in Physical, Biological Sciences, Computer Science, Computational Science or Computer Architecture, and 8 years of experience in HPC (or an equivalent combination of education and experience).
• Experience in benchmarking, code instrumentation, and performance analysis of parallel applications & workflows with an emphasis on emerging architectures. Experience with performance profiling tools, hardware performance counters and/or code instrumentation systems.
• Proven record of working effectively in a team, seeing projects through to completion, meeting deadlines, interacting with users, and thorough documentation of contributions.
• Experience with computer architecture trends and their application to High Performance Computing (HPC).
• Detailed understanding of state-of-the-art tools used to program, profile, and debug parallel scientific applications & workflows. (Such as MPI, PGAS, OpenMP, and hybrid-parallel codes using C, C++, Python, and Fortran code.)
• Demonstrated track record of research and technical publications.
• B.S. in Physical, Biological Sciences, Computer Science, Computational Science or Computer Architecture and a minimum of 12 years of experience in HPC (or an equivalent combination of education and experience).
• A demonstrated ability to lead technical efforts in a team environment.
• Nationally and or internationally recognized expertise in an HPC related discipline.
• Experience with hardware and software technologies in emerging areas, such as cloud computing and AI, and their application to HPC.
• Demonstrated a detailed understanding of HPC computer architecture technologies including CPU, memory, interconnect, parallel I/O and/or networking.
• This is a full-time career appointment, exempt (monthly paid) from overtime pay.
• This position will be hired at a level commensurate with the business needs and the skills, knowledge, and abilities of the successful candidate.
• This position may be subject to a background check. Any convictions will be evaluated to determine if they directly relate to the responsibilities and requirements of the position. Having a conviction history will not automatically disqualify an applicant from being considered for employment.
• This position accommodates US-based remote or onsite work at Lawrence Berkeley National Lab, 1 Cyclotron Road, Berkeley, CA.
How To Apply
Apply directly online at http://126.96.36.199/counter.php?id=193689 and follow the on-line instructions to complete the application process.
Equal Employment Opportunity: Berkeley Lab is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, age, or protected veteran status. Berkeley Lab is in compliance with the Pay Transparency Nondiscrimination Provision under 41 CFR 60-1.4. Click here (https://www.dol.gov/agencies/ofccp/posters) to view the poster and supplement: “Equal Employment Opportunity is the Law.”
Lawrence Berkeley National Laboratory encourages applications from women, minorities, veterans, and other underrepresented groups presently considering scientific research careers.